Recently, attention has been focused on a laminated-type (three-dimensional) semiconductor memory device as a device that can achieve high integration without being restricted by the limit of resolution of the lithography technology. In such three-dimensional semiconductor memory device, the memory cells are disposed in a laminating direction. Conducting layers extend from the respective memory cells, which are disposed in the laminating direction.
This three-dimensional semiconductor memory device has a problem that as increasing the thickness of the laminating direction, the stress generated by the laminate material increases the warping of the laminated structure.